1. Field of Invention
The present invention relates to a stacked bottom lead package in semiconductor devices and a method thereof. More specifically, comprising leads that are bent along with the circumference of the body which has been premolded wherein a chip is included inside the premolded body, the package and the method thereof according to the present invention enable a dual process and keep the solder fatigue of the lead from the heat carried via the extended lead and emitted out of the chip and decrease area required for stacking semiconductor packages.
In general, a bottom lead semiconductor package BLP type has leads lie at the bottom of the package body. A method of coupling the leads is Lead On Chip LOC, in which leads have been connected to the chip and then fixed to the chip by molding them simultaneously.
2. Discussion of Related Art
FIG. 1 shows a cross-sectional view of the bottom lead package according to the background art.
The conventional BLP consists of leads 130 fixed to the surface of a semiconductor chip 120 with an adhesive tape 140, input/output pads of the chip 120, leads 130 and bonding wires 150 wherein the portion of the inner leads of the leads 130 and the input/output pads of the chip 120 are connected electrically each other, and a molded part 110 including the bonding wire 150 and having been formed by means of pouring epoxy resin into it.
As a portion of the leads 130, outer leads are disclosed under the bottom of the molded part 110 and the bottom of the molded part 110 and the surface of the leads are located at the same plane, the BLP is mounted on a printed circuit board at which the disclosed portion of the leads 130 are soldered.
FIG. 2 is a flow chart showing the process of fabricating the BLP according to the background art.
As is shown in FIG. 2, the conventional process of fabricating the BLP comprises the steps of separating a wafer including a plurality of chips into each chip by means of cutting the wafer S10, a die bonding fixing the separated chip to a paddle of a lead frame S20, a wire bonding S30 connecting electrically the chip to the leads with bonding-wires between the input/output pads and the leads, a molding S40 forming a molded part in which the wire-bonded chip and the leads are coupled with each other in use of an epoxy resin, hardening the molded body S50, a grinding S60 eliminating the epoxy molding compound which has remained at the disclosed leads in the molding step, a plating S70 soldering the disclosed leads with protecting materials, a marking S80 giving an identification factor on a surface of the molded part, a lead trimming and a forming S90 which are eliminating an unnecessary portion of the leads out of the molded part and bending the leads according to a defined pattern, respectively.
FIG. 3A to FIG. 3B show variations of formed leads to stack semiconductor packages.
In FIG. 3A, a TSOP typed semiconductor package is formed by means of making outer leads of the upper stacked semiconductor package longer than those of the lower stacked semiconductor package.
In FIG. 3B, the leads of the stacked semiconductor packages are coupled with connecting bars 160.
The conventional BLP has been troubled with the fatigue occurring on account of the heated solder formed on the surface of the leads wherein the heating is caused by the heat emitted out of the chip and carried via leads, and the poor durability of the semiconductor resulted from the micro gap that has been caused by the shock of cutting the leads on account of the short distance between the leads and the molded part.
And the conventional method of fabricating a BLP has problems in time consuming on the whole process in consecutive order such as a process after another, and in additive process of grinding the leads to eliminate the epoxy molding compounds that has remained at the leads in molding.
Moreover, in stacking the semiconductor packages according to the conventional method, the interfaces between the outer leads protrude outward and lead bars are necessary for connecting each lead together, causing the increase of mounting area and the increased height of stacking the semiconductor packages due to the insufficient contacts between the interfaces of the leads.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.